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A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder

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Abstract

A deeply pipelined and parallel LDPC decoder architecture is proposed in this paper. The main feature of this architecture is the ∆-update scheme, which relaxes the data dependency requirement and allows for deeper pipelines than typical decoders. The proposed architecture also has the flexibility to handle a large number of codes. Frame error rate performance is shown for three codes with different quantization parameters. Finally, the impact of pipeline depth on processing time and on the energy-delay product (EDP) is evaluated from post-synthesis results. The results show that the ability to have deeper pipelines can lead to large reductions in EDP.
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Dates and versions

hal-02925057 , version 1 (28-08-2020)

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Jérémy Nadal, Mickaël Fiorentino, Elsa Dupraz, François Leduc-Primeau. A Deeply Pipelined, Highly Parallel and Flexible LDPC Decoder. Newcas 2020, Jun 2020, Montreal, Canada. ⟨10.1109/NEWCAS49341.2020.9159808⟩. ⟨hal-02925057⟩
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