When designing electronic systems, a standard technique to reduce the energy consumption consists of agressively downscaling the voltage supply. However, due to physical limitations, further reducing the power supply of next generations of electronic devices will make computational units unreliable, which may introduce faults in the computation operations realized on these chips [3]. On the other hand, tolerating faults in the computation operations gives us the opportunity to address a tradeoff between algorithm performance and energy consumption. This is the issue we consider in this talk.